Method of forming a stack of packaged memory dice

ABSTRACT

A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 11/092,348,filed Mar. 29, 2005, pending, which is a continuation of applicationSer. No. 10/634,073, filed Aug. 4, 2003, now U.S. Pat. No. 6,884,654,issued Apr. 26, 2005, which is a continuation of application Ser. No.10/154,549, filed May 24, 2002, now U.S. Pat. No. 6,656,767, issued Dec.2, 2003, which is a continuation of application Ser. No. 09/923,481,filed Aug. 6, 2001, now U.S. Pat. No. 6,465,275, issued Oct. 15, 2002,which is a continuation of application Ser. No. 09/641,574, filed Aug.18, 2000, now U.S. Pat. No. 6,329,221, issued Dec. 11, 2001, which is acontinuation of application Ser. No. 09/036,662, filed Mar. 9, 1998, nowU.S. Pat. No. 6,207,474, issued Mar. 27, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to packaged integrated circuit devices. Morespecifically, the present invention relates to an interconnected stackof packaged memory devices and the method of forming a stack ofinterconnected packaged memory devices.

2. Background of Related Art

High performance, low cost, increased miniaturization of components, andgreater packaging density of integrated circuit semiconductor devices(ICs) have long been the goals of the computer industry. Greaterintegrated circuit semiconductor device package density for a givenlevel of component and internal conductor density is primarily limitedby the space available for die mounting and packaging. For lead framemounted dice, this limitation is, to a great extent, a result of leadframe design.

In a conventional lead frame design, the lead frame includes a pluralityof leads having their ends terminating adjacent a side or edge of anintegrated circuit semiconductor device supported by the die paddleportion of the lead frame. Electrical connections are made by means ofwire bonds extending between the leads of the lead frame and the bondpads located on the active surface of the integrated circuitsemiconductor device. Subsequent to the wire bonding operation, portionsof the leads of the lead frame and the integrated circuit semiconductordevice are encapsulated in suitable plastic material to form a packagedsemiconductor device. The leads and lead frame are then trimmed andformed to the desired configuration after the packaging of thesemiconductor device in the encapsulant material.

In a Leads-Over-Chip (LOC) type lead frame configuration for anintegrated circuit semiconductor (IC) device, the leads of the leadframe extend over the active surface of the semiconductor device beinginsulated therefrom by tape which is adhesively bonded to thesemiconductor device and the leads of the lead frame. Electricalconnections are made between the leads of the lead frame and bond padson the active surface of the semiconductor device by way of wire bondsextending therebetween. After wire bonding, the leads of the LOC leadframe and the semiconductor device are encapsulated in suitable plasticto encapsulate the semiconductor device and portions of the leads.Subsequently, the leads are trimmed and formed to the desiredconfiguration to complete the packaged semiconductor device.

With ever-increasing demands for miniaturization and higher operatingspeeds, multichip module systems (MCMs) have become increasinglyattractive in a variety of applications. Generally, MCMs may be designedto include more than one type of semiconductor device within a singlepackage, or may include multiples of the same type of semiconductordevice, such as the single-in-line memory module (SIMM) or dual-in-linememory module (DIMM).

MCMs typically comprise a planar printed circuit board (PCB) or othersemiconductor carrier substrate to which a plurality of semiconductordevices is attached. Laminated substrates, such as FR-4 boards, areincluded in the term PCB as used herein, as are ceramic and siliconsubstrates, although the latter constructions are at this time lesscommon as MCM carrier substrates. The semiconductor devices aretypically wire bonded, TAB-connected or flip-chip bonded (by an array ofsolder or other conductive bumps or conductive epoxies) to the PCB. AnMCM configuration typically allows semiconductor devices to be bonded toone side only of the carrier substrate. Moreover, for semiconductordevices that are wire bonded to the PCB, the bond wires extend from thetop surface of each semiconductor device mounted on one side of the PCBby its back side to the plane of the PCB surface on the back side,requiring longer wires to be used to connect the semiconductor devicesto the PCB traces than if the active surface of the semiconductor devicewere closer to the PCB surface. This often leads to undesirableparasitic electrical characteristics. Also, mounting the semiconductordevices on a substrate to be subsequently mounted on the PCB usesvaluable area of the PCB which may be used for other purposes.Additionally, the plurality of wires used to connect the semiconductordevices to the substrate of the MCM affects the speed at which the MCMresponds when connected to the PCB.

In many instances, PCBs (such as those used in computers) have fixedsize requirements, thereby making space on the PCB scarce. Therefore, aneed exists for a high density, minimal volume configuration, and highresponse rate series of interconnected semiconductor devices for use inconjunction with a PCB.

SUMMARY OF THE INVENTION

An integrated circuit semiconductor device stack includes a stack ofpackaged integrated circuit semiconductor devices (ICs) supported by aboard or other support surface. One or more multiconductor insulatingassemblies provide an interface between terminals of the ICs andexternal circuitry. One embodiment of the multiconductor insulatingassembly includes tape (such as Kapton™ tape) on which conductors areapplied. One surface of the tape is preferably adhesive so as to stickto the ICs. When properly aligned, the conductors make contact with theterminals of the ICs and with a multiconductor port. There may bemultiple layers of conductors where different terminals of individualICs aligned in a stack are to receive different signals. Anotherembodiment of the multiconductor insulating assembly includes an epoxyonto which conductors are applied. In yet another embodiment,multiconductor insulating assembly tape is sandwiched between ICs.Contact pads on the tape are aligned with bonding pads on the ICs. Inyet another embodiment of the multiconductor insulating assembly,multiple conductors are extruded and cut to form the desiredmulticonductor assembly which is subsequently adhesively bonded to theICs with the conductors in contact with the bonding pads on the ICs.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIG. 1 is a front view of a stack of ICs on a board;

FIG. 2 is a side view of one of the ICs taken along lines 2-2 of FIG. 1;

FIG. 3 is a front view of a stack of ICs according to one embodiment ofthe present invention;

FIG. 4A is a side view of a spool of tape used in connection with FIG.3;

FIG. 4B is a top view of the tape of FIG. 4A;

FIG. 5 is a side view of a portion of FIG. 1;

FIG. 6A is a top view of a multiconductor port of FIG. 1;

FIG. 6B is a top view of an alternative multiconductor port;

FIG. 7 is an alternative embodiment to that of FIG. 5;

FIG. 8 is a cross-sectional view taken along line 8-8 of FIG. 7;

FIG. 9 is a front view of an alternative multiconductor insulatingassembly tape;

FIG. 10 is a front view of four separate conductors connected to fourterminals;

FIG. 11 is a front view of alternative means of connection betweenterminals and a multiconductor insulating assembly tape;

FIG. 12 is an alternative shape for a terminal;

FIG. 13A is a front view of an alternative embodiment of the presentinvention of a stack of ICs using a conductive epoxy;

FIG. 13B is a side view along line B-B of FIG. 13A of the presentinvention;

FIG. 14A is a front view of yet another embodiment of the presentinvention of a stack of ICs;

FIG. 14B is a bottom view of one of the ICs of FIG. 14A;

FIG. 14C is a top view of one of the multiconductor insulating assemblytapes of FIG. 14A;

FIG. 15 is a side view of a multiconductor extrusion prior to cutting amulticonductor insulating assembly therefrom; and

FIG. 16 is an end view of the multiconductor extrusion of FIG. 15 priorto cutting a multiconductor insulating assembly therefrom.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, an IC device stack assembly 10 includes a stack ofintegrated circuit semiconductor devices 14A, 14B, 14C, and 14D(collectively referred to as ICs 14) positioned on a board 18. ICs 14are illustrated as Thin Small-Outline Package (TSOP) devices, but mayhave another packaging or be unpackaged. ICs 14 may be any of a varietyof devices including, but not limited to, dynamic random access memory(DRAM), static random access memory (SRAM), programmable read onlymemory (PROM), application specific integrated circuits (ASICs), gatearrays, control devices, and microprocessors. Merely as an example, andnot a limitation, the invention may be used with a dual-in-line packagestack on a dual-in-line board. Board 18 may be any of a variety ofboards or supports including, but not limited to, a PCB. Although fourintegrated circuit semiconductor devices are shown in the IC devicestack assembly 10 of ICs, the IC device stack assembly 10 could includea greater or lesser number.

Individual integrated circuit semiconductor devices 14A and 14B may beadhered to each other through adhesive 22A. Accordingly, individualintegrated circuit semiconductor devices 14B and 14C may be adhered toeach other through adhesive 22B. Similarly, integrated circuitsemiconductor devices 14C and 14D may be adhered to each other throughadhesive 22C while integrated circuit semiconductor device 14D may beadhered to board 18 through adhesive 22D. Adhesives 22A, 22B, 22C, and22D (referred to collectively as adhesives 22) may be an adhesivelycoated tape or a suitable type liquid adhesive. If desired, adhesive 22Dmay differ from adhesives 22A, 22B, and 22C. Structural members (notshown) other than adhesive may be used to position the ICs 14 withrespect to each other, if desired.

ICs 14 include terminals 30A, 30B, 30C, and 30D (collectively referredto as terminals 30) and terminals 32A, 32B, 32C, and 32D (collectivelyreferred to as terminals 32) to interface with external electricalcomponents. Terminals 30 and 32 are illustrated as cropped lead fingers,but could have a variety of other desired shapes. Multiconductor ports36 and 38, described below, are supported by board 18.

Referring to FIG. 2, a side view of terminals 30A taken along lines 2-2of FIG. 1 is representative of side views of terminals 30B, 30C, 30D,and terminals 32A, 32B, 32C, and 32D. Terminals 30A include terminals30A-1, 30A-2, 30A-3, 30A-4, 30A-5, 30A-6, 30A-7, 30A-8, 30A-9, 30A-10,and 30A-11. Of course, a greater or lesser number of terminals may beemployed in a particular example. Further, terminals may be applied tomore than two sides of ICs 14. For example, terminals like terminals 30and 32 could be applied to all four sides of each individual IC device14.

To facilitate the interface between ICs 14 and external electricalcomponents, multiconductor insulating assemblies are connected betweenterminals 30 and multiconductor port 36 and between terminals 32 andmulticonductor port 38. The multiconductor insulating assemblies includemulticonductors, as well as insulating material therebetween to separateconductors. The insulating material may provide a pliable, flexible, yetsupportive structure to the conductors. The insulating material may beany of various materials including, but not limited to, tape and epoxy.The tape may be a polyamide resin in the form of a film (such as ismarketed by duPont under the name Kapton™). The tape may also be awell-known type of heat sensitive shrink type tape. The conductivematerials may be any of a variety of materials including copper wire,electrically conductive epoxy, such as EPO-TEK H37-MP silver filledepoxy, sold by Epoxy Technology, Inc., Billerica, Mass. 01821-3972, orthe like.

Referring to FIG. 3, multiconductor insulating assembly tape 42 includesconductors (collectively referred to as conductors 50 (FIGS. 4A, 4B))having conductive sections that interface with terminals 30A, 30B, 30C,and 30D, and with multiconductor port 36. The nature of these sectionsdepends on the structure and shape of such terminals, the structure ofmulticonductor port 36, and means of keeping multiconductor insulatingassembly tape 42 stationary with respect to the individual IC devices14A-14D and multiconductor port 36.

For example, referring to FIGS. 4A and 4B, multiconductor insulatingassembly tape 42 is referred to as Y-axis tape, because it includesstraight conductors 50 applied to a tape backing 52. Conductors 50 arealigned with a Y-axis with respect to an X-axis board 18. Multiconductorinsulating assembly tape 42 may be wrapped about a spool 48. As aportion of multiconductor insulating assembly tape 42 is unwound fromspool 48, it may be applied to the side of the stacked ICs 14,individually, 14A-14D as shown in FIG. 3. For ease in understanding, aportion of conductors 50 have been labeled 50-1, 50-2, 50-3, 50-4, . . ., and 50-11. Conductors 50 are spaced apart from one another so as toalign with respective ones of terminals 30A, respective ones ofterminals 30B, respective ones of terminals 30C, and respective ones ofterminals 30D.

Tape backing 52 preferably includes a suitable adhesive thereon so as toadhere to the side of ICs 14, individually 14A-14D. For example, asshown in FIG. 3, a portion of backing 52 makes contact with a portion ofeach of the individual ICs 14A-14D at points 56, 58, and 60.

For example, FIG. 5 shows conductors 50-1, 50-2, 50-3, . . . , and 50-11in alignment and making electrical contact with terminals 30A-1, 30A-2,30A-3, . . . , and 30A-11; and in alignment and making electricalcontact with terminals 30B-1, 30B-2, 30B-3, . . . , and 30B-11; inalignment and making electrical contact with terminals 30C-1, 30C-2,30C-3, and 30C-11; and in alignment and making electrical contact withterminals 30D-1, 30D-2, 30D-3, . . . , and 30D-11. (To avoid unnecessaryclutter in the drawing figure, not all terminals and conductors arelabeled.)

FIG. 6A shows a top view of multiconductor port 36, which includesconductive sections 66-1, 66-2, 66-3, . . . , and 66-11 spaced to alignwith conductors 50-1, 50-2, 50-3, . . . , and 50-11, respectively.

Multiconductor insulating assembly tape 44 (FIG. 3) may be substantiallythe same as or somewhat different from multiconductor insulatingassembly tape 42, and terminals 32A, 32B, 32C, and 32D may besubstantially the same as or somewhat different from terminals 30A, 30B,30C, and 30D. Further, multiconductor port 38 may be substantially thesame as or somewhat different from multiconductor port 36.

Multiconductor insulating assembly tape 42 may be cut after conductor50-11, or it may just be applied to an adjacent assembly (similar toassembly 10) or wrapped around the back of IC device stack assembly 10and applied to terminals 32A-32D.

In most situations, it is not desirable that every terminal on each ICdevice 14 receive exactly the same electrical signal. Accordingly, it isdesirable that some terminals on IC devices 14A-14D receive differentsignals. Merely as an example, for each of the individual ICs 14A-14D,terminals 30A-11, 30B-11, 30C-11, and 30D-11 could be used as enablingterminals.

Referring to FIG. 7, in such a case, merely as an example,multiconductor insulating assembly tape 42 could be cut after conductor50-10 and four separate conductors 68A, 68B, 68C, and 68D could beapplied to terminals 30A-11, 30B-11, 30C-11, and 30D-11, respectively.Merely as an example, separate conductors 68A, 68B, 68C, and 68D couldbe joined in a tape 70 (FIG. 8) with an adhesive backing strip 74thereon (the borders of which are shown in dashed lines).

Merely as one example, as illustrated in FIG. 8 (which is a side viewtaken along lines 8-8 of FIG. 7), conductor 68D would be immediatelyadjacent to conductor 68C, which would be immediately adjacent toconductor 68B, which would be immediately adjacent to conductor 68A, forthe portion of tape 70 below the respective terminal. There is aninsulating coating of conductors 68B, 68C, and 68D, or other insulationmeans between conductors. (For purposes of illustration, the relativewidths of conductors 68 and tape 70 are exaggerated.)

As another example, as shown in FIG. 9, conductors 68A, 68B, 68C, and68D could traverse different portions of adhesive backing 74 so as notto require overlap. As still another option, conductors 68A, 68B, 68C,and 68D could be completely separate, each having a different backing,or be surrounded by insulators. In the example of FIGS. 8, 9, or 10, theterminals that control chip enable could be on another portion of theICs 14, such as on the front or back (whereas terminals 30 and 32 are onthe side).

In some cases, more than one enable terminal would be required.Enablement could be controlled by addressing signals (e.g., the 2 or 3most significant bits). Further, more than merely enable terminals couldbe different from each individual integrated circuit semiconductordevice, such as IC 14A, as compared to another individual integratedcircuit semiconductor device, such as IC 14B. In such an example,various possible multiconductor insulating assemblies may be usedincluding those illustrated in FIGS. 8, 9, and 10. It is possible tohave a single multiconductor insulating assembly tape with differentlevels of conductors for different terminals. For example, when allcorresponding terminals of ICs 14A-14D (e.g., terminals 30A-2, 30B-2,30C-2, and 30D-2) are to receive the same signal, there need be only onelevel of conductor. By contrast, if the corresponding terminals of ICs14A-14D (e.g., terminals 30A-2, 30B-2, 30C-2, and 30D-2) are each toreceive different signals, then four levels of conductors may be used.FIG. 10 illustrates four separate conductors being used as analternative to that of FIG. 9.

FIG. 6B illustrates an alternative multiconductor port 36 with fourconductive sections 76A, 76B, 76C, and 76D which may be used inconnection with the devices of FIGS. 8, 9, and 10.

Referring to FIG. 11, interface between terminals 30 and conductors 50could be made with a male-female relationship. For example, femalemembers 80 could be connected to conductors 50-1 through 50-11.

Referring to FIG. 12, the terminals may have a variety of shapes. Forexample, by curving terminal 90A-1 (rather than terminal 30A-1), thereis more surface to contact a conductor.

Referring to FIG. 13A, a multiconductor epoxy assembly 102 and amultistrand insulating epoxy assembly 104 are used in an IC device stackassembly 108, which may be the same as IC device stack assembly 10except for replacing multiconductor insulating tape 42 withmulticonductor and insulating epoxy assemblies 102 and 104.

Referring to drawing FIG. 13B, multiconductor epoxy assembly 102includes a plurality of conductors 102′, each formed of suitablewell-known conductive epoxy material. Multistrand insulating epoxyassembly 104 includes a plurality of strips of nonconductive epoxymaterial 114 located between the conductors 102′. Conductors 102′, likeconductors 50 may be injected into, bombarded on, or otherwise adheredto the nonconductive epoxy material 114 forming multistrand insulatingepoxy assembly 104. Multiple layers of conductors may also be applied toor into nonconductive epoxy material 114, such as is the case wherecorresponding terminals (e.g., terminals 30A-2, 30B-2, 30C-2, and 30D-2)are not to receive the same signal. The base epoxy material ofmultistrand insulating epoxy assembly 104 may be substantially the sameepoxy material as or somewhat different from the base epoxy material ofmulticonductor epoxy assembly 102.

Referring to drawing FIG. 14A, a stack 130 of ICs that includes a stackof unpackaged ICs 132A, 132B, and 132C is illustrated. As shown in FIGS.14A and 14B, the bottom of each of the ICs 132A, 132B, and 132C (ofwhich device 132A is representative) includes bonding pads 134 thereon(which are a form of terminals). As shown in FIGS. 14A-14C, the top ofmulticonductor insulating assembly tape 136A, 136B, and 136C (of whichtape 136A is representative) includes corresponding contact pads 138connected to conductors 140. Conductors 140 make electrical contact witha multiconductor port 142 to interface with other external circuitry. Asan alternative embodiment of the present invention to the embodimentshown in FIGS. 14A-14C, the bonding pads may be located on the top ofeach of the individual ICs. One integrated multiconductor/insulatingtape assembly may service IC devices on the top and bottom of the tape.

Referring to drawing FIG. 15, in yet another embodiment of theinvention, as shown in a side view, a plurality of conductors 50-1′,50-2′, 50-3′, 50-4′, 50-5′, etc. may be formed in an extrusion ofsuitable insulating material 160. Any desired number of conductors50-1′, etc. may be formed in the extrusion in any desired matrixconfiguration. The conductors 50-1′, etc. may be any desired shape, suchas square, rectangular, etc. The matrix configuration may be of anydesired shape, such as square, rectangular, etc.

Referring to drawing FIG. 16, the plurality of conductors 50-1′, etc. inthe insulating material 160 as illustrated in drawing FIG. 15 is shownin an end view to illustrate the conductors 50-1′, etc. formed withinthe insulating material 160 to form the desired matrix of conductors.The conductor matrix may be any desired shape having any desired numberof conductors 50-1′, etc. arranged therein. The conductor matrix may becut along either lines A-A or B-B to expose a plurality of conductors50-1′, etc. to form a multiconductor flexible insulating assembly forconnection to a plurality of ICs 14. The insulating material 160 may beadhesively bonded or secured to portions of the ICs 14, as describedpreviously herein, while the conductors 50-1′, etc. may be secured inany suitable manner to the terminals 30A-1, etc. of the ICs 14, asdescribed herein, to connect the multiconductor flexible insulatingassembly to the ICs 14. In this manner, the conductors 50-1′, etc. maybe conveniently extruded in a suitable insulation material matrix andcut to the desired number and length to form the desired multiconductorflexible insulating assembly before connection to the terminals 30A-1,etc. of the ICs 14.

LOC, TAB, and flip-chip arrangements may be used in connection with thevarious embodiments of the present invention.

As used herein, the term “connect” and related words are used in anoperational sense, and are not necessarily limited to a directconnection. For example, terminals 30 are connected to multiconductorport 36, but indirectly through a conductor of a multiconductorinsulating assembly tape or epoxy.

Having thus described in detail preferred embodiments of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description, as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

1. An integrated circuit semiconductor device assembly, comprising: aboard; a multiconductor port supported by the board; a stack including aplurality of bare integrated circuit semiconductor devices supported bythe board, each of the plurality of integrated circuit semiconductordevices including, in turn, a plurality of terminals on a surfacethereof; and a plurality of multiconductor insulating assembliesincluding multiple conductive sections and flexible insulating material,the conductive sections providing conductive paths between a portion ofthe terminals of the integrated circuit semiconductor devices and themulticonductor port.
 2. The assembly of claim 1, wherein eachmulti-conductor insulating assembly includes tape.
 3. The assembly ofclaim 2, wherein the tape is from a spool.
 4. The assembly of claim 1,wherein each multi-conductor insulating assembly includes epoxymaterial.
 5. The assembly claim 1, wherein an adjacent bare integratedcircuit semiconductor device of the plurality of bare integrated circuitsemiconductor devices of the stack is adhesively secured to anotheradjacent integrated circuit semiconductor device.
 6. The assembly ofclaim 1, wherein each multi-conductor insulating assembly is positionedbetween two bare integrated circuit semiconductor devices of theplurality of bare integrated circuit semiconductor devices.
 7. Theassembly of claim 1, wherein there are a first number of bare integratedcircuit semiconductor devices in the plurality of bare integratedcircuit semiconductor devices, each bare integrated circuitsemiconductor device including a first number of the terminals, andwherein each multi-conductor insulating assembly includes a first numberof groups of conductive sections, each group of the first number ofgroups of conductive sections including a first number of conductivesections therein.
 8. The assembly of claim 1, wherein there are a firstnumber of bare integrated circuit semiconductor devices of the pluralityof bare integrated circuit semiconductor devices, each integratedcircuit semiconductor device including a first number of the terminals,and wherein each multi-conductor insulating assembly includes a firstnumber of conductive sections therein.
 9. The assembly of claim 1,wherein at least one conductive path of a multiple conductive section ofthe multiple conductive sections contacts the same terminal of each bareintegrated circuit semiconductor device of the plurality of bareintegrated circuit semiconductor devices.
 10. The assembly of claim 1,wherein a plurality of conductive paths of a multiple conductive sectionof the multiple conductive sections contact the same terminal of eachbare integrated circuit semiconductor device of the plurality of bareintegrated circuit semiconductor devices so that corresponding terminalsfrom different individual bare integrated circuit semiconductor devicesof the plurality of bare integrated circuit semiconductor devices areconnected to each other.
 11. The assembly of claim 1, wherein themulti-conductor port includes a plurality of connectors for connectionto the conductive paths of the multiple conductive sections of eachmulti-conductor insulating assembly.
 12. The assembly of claim 1,wherein the terminals are formed from tape automated bonding (TAB) tape.13. The assembly of claim 1, wherein the board is a printed circuitboard.
 14. The assembly of claim 1, wherein the bare integrated circuitsemiconductor devices include flip chip integrated circuit semiconductordevices including solder bumps thereon.
 15. An integrated circuitsemiconductor device assembly, comprising: a board; a multiconductorport supported by the board; a stack including a plurality of packagedintegrated circuit semiconductor devices supported by the board, each ofthe plurality of integrated circuit semiconductor devices including, inturn, a plurality of terminals located on opposing sides thereof; and amulticonductor insulating assembly surrounding at least two adjacentsides of the stack of a plurality of integrated circuit packages, themulticonductor insulating assembly including multiple conductivesections and flexible insulating material, the conductive sectionsproviding conductive paths between a portion of the terminals of theintegrated circuit semiconductor devices and the multiconductor port.16. The assembly of claim 15, wherein the contact pads of the first andsecond multi-conductor insulating assemblies of the plurality ofmulti-conductor insulating assemblies are connected to a multi-conductorport supported by the support surface.
 17. The assembly of claim 15,wherein the multi-conductor insulating assemblies include tape.
 18. Theassembly of claim 15, wherein each multi-conductor insulating assemblyof the plurality of the multi-conductor insulating assemblies includeepoxy.
 19. A method of forming a stack of integrated circuitsemiconductor devices comprising: providing a multi-port connectorhaving a port; providing a board; adhering a first integrated circuitsemiconductor device having a plurality of terminals thereon to theboard; adhering a second integrated circuit semiconductor device havinga plurality of terminals thereon to the first integrated circuitsemiconductor device; and connecting a multiconductor flexibleinsulating assembly between at least one terminal of a first type on thefirst integrated circuit semiconductor device to at least one terminalof the same type terminal of the second integrated circuit semiconductordevice and a terminal of the port of the multiconductor port connector.20. The method of claim 19, wherein the multi-conductor insulatingassembly includes tape.
 21. The method of claim 19, wherein themulti-conductor insulating assembly is includes epoxy.
 22. The method ofclaim 19, wherein the multi-conductor insulating assembly is extruded.23. The method of claim 19, wherein the multi-conductor insulatingassembly is an extrusion.
 24. The method of claim 19, wherein theextrusion is cut to form the multi-conductor insulating assembly. 25.The method of claim 24, wherein at least one conductor is exposed duringthe cutting of the extrusion to form the multi-conductor insulatingassembly.
 26. The method of claim 24, wherein at least two conductorsare exposed during the cutting of the extrusion to form themulti-conductor insulating assembly.
 27. The method of claim 19, whereinthe multi-conductor insulating assembly includes a plurality ofconductors separated by insulating material.